1. Field of the Invention
The present invention relates to a semiconductor device that contains a power supply chip, a semiconductor chip and a memory controller in one package.
2. Description of the Related Art
Previously, one or more chips including a semiconductor chip and a memory controller can be contained in one package through a technology called multi-chip package (MCP). A multi-chip package memory system can be mounted in a small area and is now widely used accordingly.
In such multi-chip packages, the package size is increasingly reduced. This causes two problems. The first problem is associated with the chip area that should be so sized that it can be contained within the package. The second problem is associated with the presence of many restrictions on bonding wires for electrical connection between chips in the package with package board circuit patterns. These problems are made further difficult to solve because of the presence of a power stabilizing capacitor arranged on the package board. A shortened distance between the bonding wire and board circuit pattern and the capacitor lowers the yield and elevates the cost correspondingly. Also in the semiconductor chip and the memory controller, fine patterning of devices proceeds rapidly while the cost required for fine processes is still high.
On the other hand, a peripheral circuit required for operating an internal circuit, in particular, a power supply chip for generating an internal potential, is not fine patterned sufficiently because it requires a capacitor, and so on. Accordingly, the production of such the power supply chip through fine processes increases the cost as a problem.
Over such the problems, various devises have been attempted to reduce the occupied area (see, for example, JP-A 2003-100894). In the technology disclosed in JP-A 2003-100894, a bonding pad is formed on an upper portion of a cell region and no region is prepared for bonding pad formation in the peripheral circuit to reduce the chip area.